Verifying in an HLS context for AI and ML designs
A SystemC/C++ app from a library that extends the OneSpin 360 DV-Verify platform was used by ML IP specialist NanoSemi on a 5G/WiFi project.
Archives
The road to ES Design West: Cloud-based implementation
Moving design and verification activities into the cloud poses challenges. Next month's inaugural ES Design West will offer practical guidance.
Building an ecosystem around HLS for AI and ML designs
Mentor's AI Accelerator Ecosystem adds reference designs, libraries and other forms of support around its Catapult HLS platform.
The road to ES Design West: Systems
ES Design West was created to reflect integration, even elision of tasks across the semiconductor supply chain. Here's how the program reflects the trend.
RISC-V firms aim for lower-cost design starts
Andes and SiFive attempt to lower the barriers to entry for SoC designs based on RISC-V processor cores.
The road to ES Design West: AI
AI, its system design implications and its impact on EDA tools themselves will be a key theme for ES Design West next month.
Energy-efficient implementation of machine-learning algorithms for IoT
White paper goes from general principles through to worked examples of efficient machine-learning algorithm implmentations on dedicated processor IP.
Calibre scales to 4000 nodes for faster sign off in the cloud
AMD used Calibre with optimisations implemented for cloud support to slash runtimes on high-end server processor designs.
Microsoft Azure aims to get inside SoCs with cloud security plan
Microsoft Azure aims to use royalty-free IP to build a more secure IoT and extend the reach of its cloud services.
DAC to colocate with Semicon West next year
SEMI and the Design Automation Conference (DAC) have agreed to schedule the the US event for EDA alongside Semicon West in 2020 and 2021.