power-aware debug


June 8, 2015

Formal integration enhances bug-hunting for Cadence

Following the acquisition of Jasper Design Automation last year, Cadence Design Systems is widening the target base of applications for formal verification, covering tasks from bug hunting through accelerated simulation to 'superlinting'.
October 2, 2013

IP-XACT gets design-flow extensions

Accellera has vendor extensions for IP-XACT that allow tool-specific metadata to be added to support activities such as power-aware verification and floorplanning.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
May 7, 2013

CDNLive EMEA: Cadence brings IEEE 1801 into simulation update

Cadence Design Systems has decided to embrace IEEE 1801, derived from the Unified Power Format (UPF), providing support alongside the Common Power Format (CPF).
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:

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