power-aware debug

Following the acquisition of Jasper Design Automation last year, Cadence Design Systems is widening the target base of applications for formal verification, covering tasks from bug hunting through accelerated simulation to 'superlinting'.

Accellera has vendor extensions for IP-XACT that allow tool-specific metadata to be added to support activities such as power-aware verification and floorplanning.

Cadence Design Systems has decided to embrace IEEE 1801, derived from the Unified Power Format (UPF), providing support alongside the Common Power Format (CPF).