On-demand DRC within P&R cuts closure time in half for MaxLinear
Case study describes how RF/AMS specialist used Calibre RealTime Digital within its flow for a high-end DSP SoC.
place and route
EDA with ‘AI inside’ – Mentor’s Joe Sawicki offers an insider’s view
Mentor has a host of tools - some public, some not - that leverage AI and ML. EVP Joe Sawicki has been describing the strategy behind their development.
Synopsys fuses synthesis and place-and-route to improve IC design quality and time to results
Fusion Compiler uses a single, scalable data model, updated optimization engines, and an analysis backbone based on the industry's golden sign-off tools.
Case study: Achieving earlier signoff convergence and a ‘shift left’ for P&R at Qualcomm
Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.
Fusion improves timing say Synopsys users
Early-access customers talked about their experiences with the Synopsys Fusion-based flow in a panel session at the DAC.
GlobalFoundries plays with metal gear in search for solid gains
At VLSI Symposia 2018, GlobalFoundries researchers proposed looking at the metal-gate ‘gear’ ratio as a way of improving the routability of standard cells.
Mentor targets DRC efficiencies for place-and-route with Calibre RealTime Digital
Early users of the new P&R integrated physical verification tool say time-to-sign-off was cut by 40% and above.
Cadence and Imec tape out 3nm interconnect test chip
Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
DAC 2017 preview: Plunify
Plunify will demonstrate its new Kabuto tool that recommends RTL fixes for FPGA designs at the Design Automation Conference.
Bridging the gap between IP development and qualification for P&R
Learn how to pre-empt timing and congestion issues that could arise after synthesis by using 'PlaceFirst' technology within Oasys-RTL.
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