Cadence Design Systems today (July 13) launched Joules RTL Design Studio, a new tool that aims to close further the gap between RTL and implementation using a combination of existing internal expertise and generative-AI.
The tool has two use-cases. RTL engineers can explore options for power, performance, and area as well as the congestion (PPAC) that can cause all three of those traditional specifications to be missed. Alternatively, after hand-off for implementation, Joules RTL Design Studio can be used to smooth the back-and-forth between the two stages where bugs, ECOs or other changes become necessary as a project progresses.
“This is really targeted at improving the productivity of RTL designers, specifically at helping them understand physical effects when their RTL is going to be implemented,” explained Rob Knoth, product manager group director in the Digital & Signoff Group at Cadence.
“You’re talking about the gap between very different types of engineers. The implementation engineer lives, eats and breathes things the RTL engineer typically doesn’t understand.”
So, rather than trapping the two groups in a room with a whiteboard, Joules RTL Design Studio provides feedback within a familiar RTL cockpit, whether that is for correcting code or exploring possible optimizations during ‘what if’ analysis informed by the generative AI. Or later, through translation between disciplines after an initial hand-off.
“The main aspect of the system is an intelligent RTL debug assistance system,” Knoth said.
The generative aspect of the tool draws upon Cadence’s existing AI infrastructure, notably the Cerebrus Intelligent Chip Explorer and its Joint Enterprise Data and AI (JedAI) platform. But this has been matched in a roughly 50:50 combination with existing expert knowledge from the Joules family and other Cadence products to mitigate potential errors and hallucination by the AI engine.
This combination follows a model seen as increasingly important within EDA as AI techniques continue to evolve.
At the same time, users have the option to share data as they use Joules RTL Design Studio according to constraints they themselves set ranging from not-at-all through internal-only to completely open. Knoth acknowledged that there is as yet “no one size fits all answer here”. The need to feed more design data into AI-based systems and tools is understood though faces obvious sensitivities.
Early users of Joules RTL Design Studio have, the company says, seen improvements of up to 5X in productivity and 25 per cent in the quality of results for their RTL. One of these was Japanese SoC developer Socionext.
“Our engineers were able to achieve 2-3X better productivity through analysis efficiency, significantly reducing iterations between RTL designs and implementation,” said Shunji Katsuki, general manager of the SoC System Development Division within its Global Development Group.
“Design issues were discovered earlier than they would have been with our previous front-end design process.”
Other early endorsements have come from Arm, MediaTek and Alibaba.