Chiplet-based 3DIC designs present new challenges for flows that integrate tasks from design exploration to physical verification.
Get to know more on the specific benefits of shift left and how to achieve easy adoption.
Just how much of the flow has already has 'shift left' benefit and what is fueling further progress.
The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.
Arm has used machine-learning tools supplied by the Solido group at Siemens Digital Industries Software to speed up IP validation runtime a thousand-fold compared to conventional statistical methods.
Learn how Calibre RealTime Digital allows you to identify, explore and fix DRC violations as you go.
A case study describes how the RF and AMS specialist achieved efficiencies on a complex server DSP SoC project by running as-you-go DRC during place and route.
By analyzing topology during the schematic design phase, you can detect latch-up issues before post-layout ERCs and avoid late stage revisions.
Tests on Microsoft Azure's cloud have shown Mentor's AMS simulation tools can run across thousands of processors with near-linear scaling.
AMD used Calibre with optimisations implemented for cloud support to slash runtimes on high-end server processor designs.
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