physical verification

September 8, 2022

Module verification demands integrated DRC and LVS

The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.
October 26, 2021

Arm accelerates library verification with Solido ML

Arm has used machine-learning tools supplied by the Solido group at Siemens Digital Industries Software to speed up IP validation runtime a thousand-fold compared to conventional statistical methods.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations: ,
June 21, 2021

From iterative to in-design DRC and debug for place and route

Learn how Calibre RealTime Digital allows you to identify, explore and fix DRC violations as you go.
May 14, 2021

How MaxLinear cut physical verification time with in-design DRC

A case study describes how the RF and AMS specialist achieved efficiencies on a complex server DSP SoC project by running as-you-go DRC during place and route.
January 28, 2020

Earlier latch-up prevention with topology-based analysis

By analyzing topology during the schematic design phase, you can detect latch-up issues before post-layout ERCs and avoid late stage revisions.
October 29, 2019

Mentor scales AMS cloud verification to 10,000 cores

Tests on Microsoft Azure's cloud have shown Mentor's AMS simulation tools can run across thousands of processors with near-linear scaling.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
June 6, 2019

Calibre scales to 4000 nodes for faster sign off in the cloud

AMD used Calibre with optimisations implemented for cloud support to slash runtimes on high-end server processor designs.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: , , ,
January 21, 2019

Synopsys gets big-chip signoff boost from Innovium

Data-centre networking chip goes through full-chip design rule checking and layout-versus-schematic signoff on TSMC's 16nm finFET process in a day.
January 21, 2019

Video series details the physical verification process

Physical verification challenge of large SoCs on leading-edge processes detailed in video series
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , ,   |  Organizations:
June 20, 2018

DAC 2018 preview: Mentor

Mentor will be present throughout the DAC program but with a particular focus on machine learning, artificial intelligence and automotive challenges.

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