By analyzing topology during the schematic design phase, you can detect latch-up issues before post-layout ERCs and avoid late stage revisions.
Tests on Microsoft Azure's cloud have shown Mentor's AMS simulation tools can run across thousands of processors with near-linear scaling.
AMD used Calibre with optimisations implemented for cloud support to slash runtimes on high-end server processor designs.
Data-centre networking chip goes through full-chip design rule checking and layout-versus-schematic signoff on TSMC's 16nm finFET process in a day.
Physical verification challenge of large SoCs on leading-edge processes detailed in video series
Mentor will be present throughout the DAC program but with a particular focus on machine learning, artificial intelligence and automotive challenges.
Early users of the new P&R integrated physical verification tool say time-to-sign-off was cut by 40% and above.
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