The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.
Arm has used machine-learning tools supplied by the Solido group at Siemens Digital Industries Software to speed up IP validation runtime a thousand-fold compared to conventional statistical methods.
Learn how Calibre RealTime Digital allows you to identify, explore and fix DRC violations as you go.
A case study describes how the RF and AMS specialist achieved efficiencies on a complex server DSP SoC project by running as-you-go DRC during place and route.
By analyzing topology during the schematic design phase, you can detect latch-up issues before post-layout ERCs and avoid late stage revisions.
Tests on Microsoft Azure's cloud have shown Mentor's AMS simulation tools can run across thousands of processors with near-linear scaling.
AMD used Calibre with optimisations implemented for cloud support to slash runtimes on high-end server processor designs.
Data-centre networking chip goes through full-chip design rule checking and layout-versus-schematic signoff on TSMC's 16nm finFET process in a day.
Physical verification challenge of large SoCs on leading-edge processes detailed in video series
Mentor will be present throughout the DAC program but with a particular focus on machine learning, artificial intelligence and automotive challenges.
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