September 8, 2022
The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.
October 26, 2021
Arm has used machine-learning tools supplied by the Solido group at Siemens Digital Industries Software to speed up IP validation runtime a thousand-fold compared to conventional statistical methods.
June 21, 2021
Learn how Calibre RealTime Digital allows you to identify, explore and fix DRC violations as you go.
May 14, 2021
A case study describes how the RF and AMS specialist achieved efficiencies on a complex server DSP SoC project by running as-you-go DRC during place and route.
January 28, 2020
By analyzing topology during the schematic design phase, you can detect latch-up issues before post-layout ERCs and avoid late stage revisions.
October 29, 2019
Tests on Microsoft Azure's cloud have shown Mentor's AMS simulation tools can run across thousands of processors with near-linear scaling.
June 6, 2019
AMD used Calibre with optimisations implemented for cloud support to slash runtimes on high-end server processor designs.
January 21, 2019
Data-centre networking chip goes through full-chip design rule checking and layout-versus-schematic signoff on TSMC's 16nm finFET process in a day.
January 21, 2019
Physical verification challenge of large SoCs on leading-edge processes detailed in video series
June 20, 2018
Mentor will be present throughout the DAC program but with a particular focus on machine learning, artificial intelligence and automotive challenges.