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September 21, 2020

Deliver RFIC reliability and performance through automation

Today's increasingly complex and integrated RFICs pose complex verification challenges best addressed before costly simulation runs.

Article | Topics: Verification | Tags: calibre, fill, layout, layout dependent effects, RFIC, shallow trench isolation, topology, well proximity | Organizations: Siemens EDA

April 13, 2016

User2User preview: Silicon Valley edition rolls out this month

Companies presenting at User2User Santa Clara on April 26 include AMD, Microsoft, nVidia, Oracle, Qualcomm, and Samsung.

Article | Topics: Conferences, Design to Silicon, Digital/analog implementation, Blog - EDA, - GDSII, Blog - PCB, - RTL, Tested Component to System, Verification | Tags: emulation, fill, floorplanning, formal verification, multi-die package, portable stimulus, structured test | Organizations: AMD, Arm, Mentor Graphics, Micron Technology, Microsemi, Microsoft, nVidia, Oracle, Qualcomm, Samsung Electronics, User2User, Xilinx