Tested Component to System

March 19, 2020

Deploying pre- and post-silicon verification and test for 5G designs

A flexible and still evolving range of 5G standards requires methodologies that can handle massive test.
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December 16, 2019

Mentor delivers eMRAM test for ARM/Samsung FDSOI at 28nm

Tessent test suite targets automotive, AI and IoT projects that need embedded non-volatile memory.
October 4, 2019

Master the design and verification of next gen transport: Part Three – functional safety

The third part of this series takes the original CNN demonstrator through a full ISO 26262 type functional safety workflow
May 27, 2019

Automotive complexity drives DFT to the RTL

Design-for-test can no longer be left until the gate level for increasingly sensitive designs aimed at newer processes.
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April 18, 2019

User2User Silicon Valley is two weeks away

Mentor's technical conference will take place on May 2 at the Santa Clara Marriott and feature more than 45 user and vendor presentations.
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April 16, 2019

Boost your DFT efficiency for AI silicon design

Three hierarchical DFT strategies help cut time-to-market for large AI chips by exploiting regularity and addressing test at the RTL.
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February 18, 2019

How to optimize your testbench-to-DUT connections

Testbench connections often depend on the virtual interface feature of SystemVerilog but other options - like abstract classes - can help.
October 29, 2018

Mentor extends Tessent for debug and automotive pattern generation

As ITC 2018 begins, Mentor addresses stringent ISO 26262 requirements and looks to bridge the gap in how IJTAG-based debug is structured.
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April 10, 2018

Control test point counts for ISO 26262

The automotive safety standard targets 90% in-system test coverage. VersaPoint technology helps to simplify reaching your target.
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March 9, 2018

DATE 2018 preview: Mentor

DATE highlights for Mentor include a 90-minute workshop on achieving functional safety for autonomous driving.

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