Humans have always had an innate attraction to symmetry (Figure 1). Egyptian pharaohs amazed the world by the perfect proportions of their huge pyramids. During the Renaissance, Leonardo da Vinci gave us Vitruvian Man, an ideal based on the architectural concepts espoused centuries earlier by engineer and architect Marcus Vitruvius Pollio. The pharaohs, Vitruvius, and da Vinci all clearly understood the importance of proportions and symmetry in design—concepts that are still respected in architecture and art today. In our modern world, symmetry detection is now widely used in applications that involve image processing, such as facial recognition, fingerprint sensors, object recognition, etc. These applications focus on identifying multiple types of physical symmetry, and have been competing to leverage the state-of-art speed and quality of processing algorithms.
Very large-scale integration (VLSI) design flows also use symmetry, but not just to make the resulting chip beautiful. Symmetry in integrated circuit (IC) design is crucial for both physical and operational reliability, as well as accurate circuit performance and high-yield manufacturing. Historically, however, symmetry verification has been limited to ensuring compliance with electrical matching requirements. This is traditionally covered by layout design techniques such as 1D multi-finger device interdigitation and its 2D counterpart, common centroid implementation. Both techniques deliver consistency of electric currents in each device finger by ensuring the same resistance in all interconnect paths, layers, and vias leading to the source and drain of these devices. Although these techniques are easy to understand, there have always been challenges with their associated implementation, checking, and especially, debugging of the subtle differences that often arise from non-intuitive sources (e.g., a shifted via or a corner case of misconnection of abutment on a drawn layer).
Moreover, as technology nodes have advanced, the increases in both design complexity and process requirements imply or require types of symmetries that are no longer limited to the simple geometrical aspects of a drawn layout. The expanded role of symmetry across the entire design cycle includes the new symmetry challenges and requirements of design types such as analog, radio frequency (RF), and memories, as well as their associated applications (e.g., Internet of Things, automotive and 5G). In addition, advanced processes create manufacturing-related symmetry process requirements for fill and multi-patterning. The new VLSI needs for symmetry, and the way in which the definition and use model for symmetry have evolved to cover the complete design cycle from the floorplanning stage to fabrication and packaging, require new symmetry verification strategies and technologies.
Siemens EDA has introduced an innovative technology using pattern/property-aware analysis in a generic methodology that cohesively satisfies all types of symmetry requirements across design and manufacturing flows (Figure 2). The basics of exact symmetry are included, as are the advanced requirements of fuzzy symmetry in designs such as memory, micro-electromechanical systems (MEMS), silicon photonics, and analog/RF, where the symmetry checking specification is often tweaked to reflect the ability of a design to tolerate PVT fluctuations (design corners).
The technology also incorporates electrically-aware symmetry that takes symmetry verification beyond currently available techniques used to ensure clock (CLK) symmetry in digital designs and differential pairs symmetry and matching in both analog and digital designs. The Calibre nmPlatform actually creates two parallel views of each pattern to map electrical aspects (topologies, voltage domains, and other circuit aspects) to the geometries, whether they are part of a simple single-layer pattern or a complex multi-layer pattern, such as a FINFET device, inductor, SRAM, or a block (e.g., a sense amplifier in memory arrays).
The Calibre nmPlatform leverages the functionality of its toolsuite to glean information from different design phases, then consolidates and cross references this data on the physical layout mask to ensure compliance with both electrical and reliability requirements and guidelines (Figure 3). The symmetry verification flow can be invoked in either batch mode (controlled by an XML interface that enables easy constraint setting for big blocks and full chips) or a simple interactive checking, debugging, and fixing process using the Calibre RealTime interfaces, which are integrated into all major design environments.
Symmetry is not just pleasing to look at—it is a critical success factor for today’s complex and varied IC designs. Designers must be able to verify symmetry requirements starting from placement issues in floorplanning, to context-aware symmetry requirements in layout verification, to multi-patterning and fill impacts for fabrication. Innovative symmetry verification techniques implemented in existing EDA tools like the Calibre nmPlatform enable design teams to quickly and accurately find and correct symmetry issues before they can impact tapeout schedules or product quality.
For a full discussion of the advanced symmetry checking available in the Calibre nmPlatform, download the technical paper, Advanced symmetry checking in IC layout design and verification.