Aldec has updated its Riviera Pro tool to provide more support for OS-VVM, the recently launched verification methodology for VHDL
Until the software is ready, it's often hard to tell when two neighbouring units on an SoC could combine to push the package past its maximum thermal point. Docea Power aims to help.
Blue Pearl Software has extended its reach into the world of field-programmable gate array (FPGA) design and verification with a project that has culminated in a tighter integration between its timing analysis tools and the Synopsys Synplify Pro tool.
Robert Bosch is expecting to see major growth in electronics in cars over the coming decade. But most of that growth will not be coming from electric vehicles of the four-wheeled variety, said the company's automotive division president.
Old processes don't necessarily equate to old tools, panelists argued at DATE, especially when a lot of future work will be done on more-than-Moore, 3DIC technologies.
DATE panelists discuss three ways to tackle design complexity: by moving to higher levels of abstraction; by making more subtle use of existing synthesis strategies; and by better organisation.
The CTO of one European design house wants better acceleration features from analog design tools, not automation that overrides their judgement.
Concern over energy consumption could be the key to European companies moving back into the compute server market – or at least that's what the European Commission and researchers think is possible as social networks, GPS data and public video cameras pour data into a growing collection of online storage banks.
Collaboration is becoming increasingly important to foundry companies as the development of advanced process nodes becomes more complex
Can pattern recognition improve deign rule checking at advanced nodes?
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