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March 10, 2015

Cadence reworks implementation for both finFET and older processes

Cadence Design Systems has coupled the parallel-processing techniques behind its recently launched sign-off tools to engines intended to deal with sub-28nm process issues in a suite that reworks the company’s key implementation tools.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
November 24, 2014

A57 finFET design underlines routing challenges

In a presentation at the recent ARM TechCon, HiSilicon described the issues in putting together a 16nm finFET-based design built around a cluster of ARM’s Cortex A57 processors.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: ,
August 18, 2014

Power and clocking at 20nm force changes in FPGAs

Design for the 20nm generation of processes has revealed power and clocking issues for the two major FPGA manufacturers presentations at Hot Chips revealed.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: ,
July 9, 2013

Xilinx tapes out for first of 20nm-generation FPGAs

Xilinx aims to be first of the FPGA makers to produce 20nm devices, expecting to move to production samples for some products by the end of the year.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , , , ,   |  Organizations:
February 6, 2013

GlobalFoundries inks IP deals

GlobalFoundries has signed deals to let the foundry offer power-saving clocks, a massively parallel floating-point processor and interface IP from Rambus. They are "uncommon solutions" to come from a foundry, the company claims.

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