clock tree

Cadence Design Systems has coupled the parallel-processing techniques behind its recently launched sign-off tools to engines intended to deal with sub-28nm process issues in a suite that reworks the company’s key implementation tools.

In a presentation at the recent ARM TechCon, HiSilicon described the issues in putting together a 16nm finFET-based design built around a cluster of ARM’s Cortex A57 processors.

Design for the 20nm generation of processes has revealed power and clocking issues for the two major FPGA manufacturers presentations at Hot Chips revealed.

Xilinx aims to be first of the FPGA makers to produce 20nm devices, expecting to move to production samples for some products by the end of the year.

GlobalFoundries has signed deals to let the foundry offer power-saving clocks, a massively parallel floating-point processor and interface IP from Rambus. They are "uncommon solutions" to come from a foundry, the company claims.