Microsemi has put multiple RISC-V cores into a new generation of SoC FPGAs, intended for embedded systems that need to run Linux.
The RISC-V workshop in California at the end of November 2017 provided the opportunity for Western Digital to commit its own work on processors for internal use to the open-source architecture and for the ecosystem of off-the-shelf cores and tools to expand.
Microsemi has set up an ecosystem program around the RISC-V soft cores the company has designed for its FPGAs.
Semiconductor supplier Microsemi has used the Eclipse open-source IDE platform to develop a Windows-based toolchain for CPUs that supports the RISC-V instruction set.
The major verification conference is looming and Mentor's participation will include tutorials that explore the latest in portable stimulus, SystemC, VIP and more.
Microsemi has launched a family of non-volatile FPGAs that use a 28nm process to increase density over the previous SmartFusion devices.
Companies presenting at User2User Santa Clara on April 26 include AMD, Microsoft, nVidia, Oracle, Qualcomm, and Samsung.
Open-source hardware, in-field configurability, and a hardware-plus-services approach could protect margins as the IoT hammers down costs, says GSA report.
Design security is a major target for Microsemi’s update to its Igloo series of flash memory-based FPGAs, which add an ARM-oriented memory subsystem.
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