Cadence uses reinforcement learning to tune flow
Cadence has launched a tool that the company claims can speed up implementation by applying machine learning across the flow.
physical implementation
Mentor tunes LVS for early SoC integration
Mentor has released a tool that attempts to deal with the problems encountered in the use of physical circuit verification in the early stages of SoC integration.
ES Design West registration opens
Registration has opened for the first ES Design West exhibition, which takes place alongside Semicon West in San Francisco in July.
Fusion improves timing say Synopsys users
Early-access customers talked about their experiences with the Synopsys Fusion-based flow in a panel session at the DAC.
Remember the design gap? It’s back
Fifteen years on from the design gap that triggered the IP revolution, implementation costs have created a new one.
Cadence cuts up DRC for speed
Cadence Design Systems has launched a design-rule checking engine that can distribute its workload across multiple servers in a cloud, private farm or mixture of both to speed up signoff.
Bridging the gap between IP development and qualification for P&R
Learn how to pre-empt timing and congestion issues that could arise after synthesis by using 'PlaceFirst' technology within Oasys-RTL.
PLATINUM SPONSORS
View All Sponsors