Mentor has released a tool that attempts to deal with the problems encountered in the use of physical circuit verification in the early stages of SoC integration.
Registration has opened for the first ES Design West exhibition, which takes place alongside Semicon West in San Francisco in July.
Early-access customers talked about their experiences with the Synopsys Fusion-based flow in a panel session at the DAC.
Fifteen years on from the design gap that triggered the IP revolution, implementation costs have created a new one.
Cadence Design Systems has launched a design-rule checking engine that can distribute its workload across multiple servers in a cloud, private farm or mixture of both to speed up signoff.
Learn how to pre-empt timing and congestion issues that could arise after synthesis by using 'PlaceFirst' technology within Oasys-RTL.
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