physical implementation


July 20, 2020

Mentor tunes LVS for early SoC integration

Mentor has released a tool that attempts to deal with the problems encountered in the use of physical circuit verification in the early stages of SoC integration.
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March 15, 2019

ES Design West registration opens

Registration has opened for the first ES Design West exhibition, which takes place alongside Semicon West in San Francisco in July.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: ,
July 3, 2018

Fusion improves timing say Synopsys users

Early-access customers talked about their experiences with the Synopsys Fusion-based flow in a panel session at the DAC.
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June 27, 2018

Remember the design gap? It’s back

Fifteen years on from the design gap that triggered the IP revolution, implementation costs have created a new one.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: , ,
April 12, 2017

Cadence cuts up DRC for speed

Cadence Design Systems has launched a design-rule checking engine that can distribute its workload across multiple servers in a cloud, private farm or mixture of both to speed up signoff.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
April 6, 2017

Bridging the gap between IP development and qualification for P&R

Learn how to pre-empt timing and congestion issues that could arise after synthesis by using 'PlaceFirst' technology within Oasys-RTL.

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