User2User preview: Silicon Valley edition rolls out this month

By Paul Dempsey |  No Comments  |  Posted: April 13, 2016
Topics/Categories: Conferences, Design to Silicon, Digital/analog implementation, Blog - EDA, - GDSII, Blog - PCB, - RTL, Tested Component to System, Verification  |  Tags: , , , , , ,  | Organizations: , , , , , , , , , , ,

The Silicon Valley edition of Mentor Graphics’ User2User conference series will take place on Tuesday, April 26th, just under a fortnight from now. As in previous years, the venue for the free-of-charge event is the Santa Clara Marriott. Registration is now open at the link above.

This year’s keynote speakers are Mentor chairman and CEO Wally Rhines, who will look at the impact of continuing M&A in the electronics sector, and Zach Shelby, vice president of marketing for the Internet of Things at ARM. A lunchtime panel will consider what might form the next big set of drivers for the industry.

However, User2User is primarily about companies sharing war stories from designs completed and in process.

User2User experiences

Some of the Mentor users that will be outlining their experiences and successes in Santa Clara include:

  • AMD: How it has applied structured-test techniques to traditional ATPG and Cell-Aware ATPG flows, as well as verification flows, and the enhancements it has realized.
  • Micron: It will discuss its experience with emulation in creating a full environment for the debug of SSD controller designs, and its future plans for exploiting the technique.
  • MicroSemi: How it applied formal verification techniques to create a rigorous, pre-code check-in review process that prevents bugs from infecting master RTL.
  • Microsoft: How it used portable stimulus to increase productivity, automate the creation of high-quality stimulus, and raise design quality.
  • Oracle: How it used it advanced fill techniques to improve manufacturing yield.
  • Qualcomm: How it used emulation for better RTL design exploration for power, leading to more accurate power analysis and sign-off at the gate level.
  • SanDisk: It will describe a methodology for the modeling and simulation of highly integrated multi-die package designs.
  • Xilinx: How it built a custom ESD verification methodology on the Calibre platform.
  • Finally here, both Samsung and nVidia will discuss how they are using new automatic RTL floorplanning capabilities on advanced SoC designs.

These and other papers that will feature across nine different tracks at the conference can be reviewed online here.


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