April 6, 2017
Learn how to pre-empt timing and congestion issues that could arise after synthesis by using 'PlaceFirst' technology within Oasys-RTL.
March 9, 2016
Mentor Graphics' recent deal with ARM illustrates how proliferation in design is influencing deals between tool and IP vendors.
June 23, 2015
The latest release of the SonicsGN NoC infrastructure provides speedups for multichannel memories.
June 3, 2015
RTL synthesis has joined the array of tools developed by Cadence Design Systems that employ distributed processing, with the aim of exploring more ways of creating area- and power-efficient logic blocks.
January 5, 2015
SystemC coding style can lead to excessive congestion in the logic generated by high-level synthesis. Cadence described how it is attacking the issue at its recent Front-End Design Summit.