mature nodes


March 10, 2015

Cadence reworks implementation for both finFET and older processes

Cadence Design Systems has coupled the parallel-processing techniques behind its recently launched sign-off tools to engines intended to deal with sub-28nm process issues in a suite that reworks the company’s key implementation tools.
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April 9, 2013

New tools reinvigorate older processes

At DATE 2013, Synopsys senior vice president Antun Domic, described how techniques for the latest nodes are being rolled back into mature nodes, all the way to 180nm.
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