IP-XACT gets design-flow extensions
EDA standards group Accellera Systems Initiative (Accellera) has developed a set of vendor extensions for IP-XACT that allow tool-specific metadata to be added to standards-compliant descriptions of IP core features, functions and interfaces to help generate area estimates and scripts for power-aware verification.
The vendor extensions published by Accellera provide recommended ways to enable cross-company IP-XACT usage in areas of design such as analog/mixed-signal, physical design planning and power.
The addition of AMS vendor extensions by Accellera expands the scope of IP-XACT to include analog/mixed-signal/digital IP, enabling designers to describe electronic metadata in various flows as well as generate hardware description language structures such as Verilog-AMS or SystemC AMS. The newly defined vendor extensions also support the description of power information to generate files that target the Common Power Format (CPF) and the Unified Power Format (UPF). Finally, the Accellera vendor extensions also enable descriptions of area estimates for the purpose of physical design planning.
These vendor extensions are fully compatible with the IEEE IP-XACT standard and available in XML format for download under an Apache 2.0 open source license.
An in-depth tutorial “Verification and Automation Improvement Using IP-XACT”, originally presented at the Design and Verification Conference, provides technical details about the standard. The IEEE 1685-2009 IP-XACT standard is available in PDF format through the IEEE Get program for download at no charge.
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