DATE notebook: Help for heat-sensitive chips

By Chris Edwards |  No Comments  |  Posted: March 16, 2012
Topics/Categories: Conferences, Design to Silicon, ESL/SystemC  |  Tags: , , , , , ,

Amid all the sleepy, dark silicon on many of today’s system-on-chip (SoC) designs, hotspots remain a problem and are becoming tougher to spot before the actual silicon makes it back from the fab. Until the software is ready, it’s often hard to tell when two neighbouring units will be active at the same time, potentially pushing the package past its maximum thermal point.

Automotive-industry users outlined similar issues at DATE even when their target devices have reasonably predictable heat-generating behaviour. The problem is when it comes to modelling how a high-voltage driver firing an airbag, and probably more than one, will affect the timing of other on-chip logic circuits as the entire die and package suddenly heats up.

High-level tools are beginning to appear that are designed help with the modelling of hotspots. Docea Power launched its AceThermalModeler (ATM) product a couple of weeks ago that lets designers estimate how heat will dissipate through the silicon and package based on what’s active at any one time.

Sylvain Kaiser, CTO of Docea, explained in a meeting at DATE this week how the tool can be used. As a product it does not, as yet, work with something like a SystemC simulation to predict how changing activity will affect the heat gradients across a die or package. That work is underway. But, for the moment, the main aim is to provide a way for designers to gauge the sensitivity of a chosen package and floorplan to heat-generated problems.

“Designers want to ensure that each device does not exceed the maximum operating condition or the maximum temperature defined by the equpiment suppliers, and that the thermal issues do not then cause mechanical issues, ” said Kaiser. “We don’t want to model elements as tiny as transistors. We want the architects to have a good overview of the thermal behaviour of the architecture”

The first step is to import layout data, said Kaiser: “We use the IC floorplan. This can be extracted from DEF. We also take into account a description of the package and the board. We only need rough descriptions. We want to draw the dynamic profile over time and model the thermal capacitance of physical elements such as the package and board over a long period of time – from seconds to minutes.

“People can use step changes in power to parts of the design to observe the reaction of the system to temperature. This probably won’t represent the real system but it allows them check the sensitivity to heat.”

Power profiles for can be imported by ATM from existing IP using reports created by characterization tools, Kaiser said.

As well as work on SystemC simulation, Docea is working on tighter links with in-circuit emulation in a project with another French startup. “Validate not just with SystemC but the real hardware and still see that you are on track with the thermal and power budget,” said Kaiser.

The emulation and simulation together may identify unexpected and problematic thermal behaviour. “Maybe there’s a mismatch between software and hardware. A register being hit too often by software. Most of the time, these problems can be fixed through software changes,” Kaiser explained, but will stop a nearly complete device making it into the market and then failing when the same pathological condition arises.

Docea will also be demonstrating ATM at the SNUG Synopsys User Group meeting in Silicon Valley later this month.

Click here for more of our coverage of DATE 2012

 

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