floorplanning


April 6, 2017

Bridging the gap between IP development and qualification for P&R

Learn how to pre-empt timing and congestion issues that could arise after synthesis by using 'PlaceFirst' technology within Oasys-RTL.
April 13, 2016

User2User preview: Silicon Valley edition rolls out this month

Companies presenting at User2User Santa Clara on April 26 include AMD, Microsoft, nVidia, Oracle, Qualcomm, and Samsung.
March 10, 2015

Cadence reworks implementation for both finFET and older processes

Cadence Design Systems has coupled the parallel-processing techniques behind its recently launched sign-off tools to engines intended to deal with sub-28nm process issues in a suite that reworks the company’s key implementation tools.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
May 20, 2014

Cadence signs with ARM for core optimizations

Cadence Design Systems has signed up for a licence to ARM cores that will let the EDA supplier optimize support for 32bit and 64bit Cortex processors in its tools.
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , , , , ,   |  Organizations: ,
October 2, 2013

IP-XACT gets design-flow extensions

Accellera has vendor extensions for IP-XACT that allow tool-specific metadata to be added to support activities such as power-aware verification and floorplanning.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
March 16, 2012

DATE notebook: Help for heat-sensitive chips

Until the software is ready, it's often hard to tell when two neighbouring units on an SoC could combine to push the package past its maximum thermal point. Docea Power aims to help.

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