System Technology Co-optimization raises various SI, PI, thermal, mechanical and warp risks due to its use of advanced packaging. Early-stage prototyping mitigates them.
Cadence has built a unified database to support a group of tools to support the planning and implementation of 3DIC designs.
A de facto standard for exchanging thermal information about designs has become JEDEC standard JEP181.
Moortec has reworked its thermal-sensing core design to allow for finer-grained use on SoCs being designed for the 5nm node.
Cadence has followed its launched of a parallelizable EM simulator with one that focuses on the thermal behavior of ICs through to multi-PCB assemblies.
Early access to tools for new processes is helping Moortec deliver IP to determine the real-time health of on-chip circuits.
Start-up Baum is co-located with Verific at DAC 2017 and will demonstrate its soon-to-launch power analysis and modeling software.
Mentor, a Siemens business, has formed an alliance with foundries and OSAT providers and launched a flow that brings IC and package design together.
Japanese giant uses variable thermal simulation on automotive IC intended for harsh environments.
Computational fluid dynamics now addresses more of the simulation activities required for complex systems in a single methodology.
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