How digital twin evaluations optimize STCO-based design

By TDF Editor |  No Comments  |  Posted: February 8, 2022
Topics/Categories: Digital Twin, Blog - EDA, - Next Generation Design, Verification  |  Tags: , , , , , , , , , , , , ,  | Organizations:

System Technology Co-optimization (STCO) is one of the hot topics in electronics design. In broad terms, it is about the partitioning of an SoC into chiplets that can be designed in parallel or taken off-the-shelf from, typically, a foundry. This mosaic is then reintegrated in a 2.5D or 3D format using an interposer often based on high-density advanced packaging (HDAP) techniques.

STCO is in many ways the latest evolution beyond Design Technology Co-optimization (DTCO). It is intended to keep the industry on a Moore’s Law performance and economics pathway as classical scaling techniques offer diminishing benefits.

However, it ain’t easy. As greater emphasis falls on system scaling and system packaging, further challenges inevitably emerge in such areas as power and signal integrity as well as thermal, warp and mechanical stress. It then follows that the later any issues are uncovered, the harder still they are to fix because of the inherent extra complexity STCO requires.

A new technical paper proposes the mitigation of the risk of late-stage errors using a ‘shift left’ to prototype and evaluate a system based on a multi-physics analysis.

Using a System Technology Co-Optimization (STCO) Approach for 2.5/3D Heterogeneous Semiconductor Integration’ describes a process by which a design can construct a digital twin – or in reality multiple digital twins reflecting the wide range of partitioning and integration options that exist for any chiplet-based design.

By doing this, the integration team can review its options for PI, SI and the other challenges HDAP strategies present, and loop back the results to the various chiplet design teams so that they produce work that is more optimized and less risky when it is passed back forward for final STCO integration.

Full verification of the 2.5D/3D results will still be necessary but the likelihood that this will uncover major issues in the project will, author Per Viklund of Siemens EDA argues, be greatly reduced.

“Solutions derived in package prototyping, guided by multi-physics analysis, is handed back to the silicon teams to help drive IP partitioning and enable the IC design teams to make better, more edu[1]cated decisions at a stage where partitioning can be changed before the design is too far along and costs of fixing problems become prohibitive,” Viklund writes.

“In other words, make decisions earlier: shift left.”

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