multicore

Imperas Software has worked with AI specialist Tenstorrent to create and distribute a model of the Ascalon processor core.

Determining which embedded technique to adopt is more than just a question of what cores the system has.

At the recent Embedded World show and conference, Colin Walls of Siemens tackled the choices facing software developers working with multicore SoCs.

In a panel session at VLSI Symposia, AMD described how the economics have come down strongly in favor of multichip integration for multicore server processors.

Siemens has agreed to acquire UK-based debug and on-chip instrumentation startup UltraSoC and will fold the operation into Mentor’s Tessent test-software product line.

Moortec has reworked its thermal-sensing core design to allow for finer-grained use on SoCs being designed for the 5nm node.

Six papers, a dedicated automotive sessions and demos including the use of the Nucleus for RISC-V are among highlights in Mentor's Embedded World agenda.

UltraSoC has increased the capacity of its embedded analytics architecture to encompass large-scale manycore architectures.

Following deals with Imperas and Percepio, UltraSoC has released an IDE aimed at debug, run control, performance tuning and runtime analytics for SoC development.

ARM, Xilinx, Cadence Design Systems, and TSMC have agreed to produce a test chip for the CCIX project.