IEEE1149.1


September 9, 2013

SoC design gets hierarchical test strategy, improved compression; system design gains end-to-end IJTAG integration strategy

Synopsys automates standards-based hierarchical test insertion and improves test compression for SoCs; Mentor teams with ScanWorks for system-wide IJTAG.
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , , , ,   |  Organizations: , ,

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