power integrity

January 17, 2017

DesignCon 2017 preview: Mentor Graphics

DesignCon 2017 takes place from Jan 31 to Feb 2 at the Santa Clara Convention Center with its usual focus on PCB design and implementation.
July 11, 2016

Mentor’s PADS family extended for AMS, DDR and electrical DRC

Mentor Graphics has added four new units to its PADS PCB family addressing increasing complexity in mainstream design.
Article  |  Topics: Blog - PCB, - Product  |  Tags: , , , , , , ,   |  Organizations:
April 4, 2016

HyperLynx made broader and easier to use

HyperLynx from Mentor Graphics has moved into a new generation with more integrated features beyond PI and SI, and an easier to use GUI.
January 14, 2016

DesignCon 2016 preview: Mentor Graphics

HyperLynx leads the way for vendor at DesignCon with booth demos and a day-long modeling and analysis seminar.
May 18, 2015

Vehicle ethernet adds to IP virtual reference kits for board design

Automotive ethernet is the latest virtual reference design platform to be added to the family of models developed by Cadence to support its physical-layer IP cores.
Article  |  Topics: Blog - IP, PCB  |  Tags: , , , , , ,   |  Organizations:
March 24, 2015

Mentor unites chip-to-package flow with Xpedition Package Integrator

Flow draws on existing strengths in Xpedition, Valor, Nimbic and Flotherm among others to optimize 3D design projects and improve cross-disciplinary communication.
January 28, 2015

Cadence updates Sigrity tools and license options

Cadence Design Systems has added LPDDR4 support and a topology explorer to its Sigrity lineup for signal and power integrity analysis of PCB-based designs, as well as more flexible licensing options.
Article  |  Topics: Blog - PCB  |  Tags: , ,   |  Organizations:
September 29, 2014

Heat becomes design assist for power supply layout

To make a high-efficiency power supply XP Power used heat as an additional design variable with an architecture that turns conventional wisdom over one aspect of component reliability on its head.
Article  |  Topics: Blog - PCB  |  Tags: , ,
August 13, 2014

Thermal limits challenge Hot Chips power pair

Two of the custom designs presented at the 26th Hot Chips in Cupertino exemplified the problems caused by increasing power density and the benefits of looking at heat removal at the system level.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,
August 5, 2014

Cadence takes Voltus to transistor level

Cadence Design Systems has introduced a variant of Voltus that runs transistor-level simulations to check for electromigration and IR-drop problems.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:

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