UltraSoC

December 11, 2019

Support for RISC-V expands at summit

This week’s RISC-V Summit in California has seen an expansion to the open-source portfolio being built around the architecture as well as increased support from software vendors such as Wind River.
October 8, 2019

UltraSoC adds security checks to bus monitoring IP

UltraSoC has developed a bus monitor that will terminate transactions if it detects behavior that breaks rules set by a system designer.
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February 18, 2019

UltraSoC scales up debug architecture

UltraSoC has increased the capacity of its embedded analytics architecture to encompass large-scale manycore architectures.
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October 17, 2018

UltraSoC combines tools for cross-SoC debug and analysis

Following deals with Imperas and Percepio, UltraSoC has released an IDE aimed at debug, run control, performance tuning and runtime analytics for SoC development.
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May 1, 2018

Andes teams with Imperas and UltrasoC for RISC-V

Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
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January 28, 2018

UltraSoC delivers trace for RISC-V

UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , ,   |  Organizations:
December 1, 2017

Workshop sees the RISC-V ecosystem expand

The RISC-V workshop in California at the end of November 2017 provided the opportunity for Western Digital to commit its own work on processors for internal use to the open-source architecture and for the ecosystem of off-the-shelf cores and tools to expand.
June 19, 2017

UltraSoc donates trace format to RISC-V group

UltraSoc has donated to the RISC-V Foundation a specification for processor trace to try to provide the ecosystem with a common way of exporting runtime data to software tools.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , , ,   |  Organizations: ,
December 7, 2016

HiSilicon licenses onchip debug engine for SOCs

HiSilicon has licensed UltraSoC’s semiconductor IP to build into SoCs for system monitoring, analysis, and optimization.
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November 24, 2016

Codasip adopts UltrasSoC debug for RISC-V cores

Codasip, a provider of processor cores based on the open-source RISC-V processor IP, has teamed up with UltraSoC to incorporate hardware debug and security features.
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