This week’s RISC-V Summit in California has seen an expansion to the open-source portfolio being built around the architecture as well as increased support from software vendors such as Wind River.
UltraSoC has developed a bus monitor that will terminate transactions if it detects behavior that breaks rules set by a system designer.
UltraSoC has increased the capacity of its embedded analytics architecture to encompass large-scale manycore architectures.
Following deals with Imperas and Percepio, UltraSoC has released an IDE aimed at debug, run control, performance tuning and runtime analytics for SoC development.
Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.
The RISC-V workshop in California at the end of November 2017 provided the opportunity for Western Digital to commit its own work on processors for internal use to the open-source architecture and for the ecosystem of off-the-shelf cores and tools to expand.
UltraSoc has donated to the RISC-V Foundation a specification for processor trace to try to provide the ecosystem with a common way of exporting runtime data to software tools.
HiSilicon has licensed UltraSoC’s semiconductor IP to build into SoCs for system monitoring, analysis, and optimization.
Codasip, a provider of processor cores based on the open-source RISC-V processor IP, has teamed up with UltraSoC to incorporate hardware debug and security features.
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