UltraSoC

June 23, 2020

Mentor to use UltraSoC acquisition to drive in-life learning

Siemens has agreed to acquire UK-based debug and on-chip instrumentation startup UltraSoC and will fold the operation into Mentor’s Tessent test-software product line.
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May 14, 2020

The price of reliability is constant vigilance

Papers presented at the recent IRPS conference showed the growing importance of lifetime monitoring to the problem of handling components as they age.
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April 16, 2020

IP partnership aims to crack down on physical hacks

UltraSoC and Agile Analog have teamed up to build an infrastructure that can help guard against physical attacks on SoCs.
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February 14, 2020

Debug connects with manufacturing test to cut product recall costs

UltraSoC has kicked off a collaboration with PDF Solutions to build a system better able to use runtime information to identify devices that are likely to fail in the field and so reduce the impact of product recalls.
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December 11, 2019

Support for RISC-V expands at summit

This week’s RISC-V Summit in California has seen an expansion to the open-source portfolio being built around the architecture as well as increased support from software vendors such as Wind River.
October 8, 2019

UltraSoC adds security checks to bus monitoring IP

UltraSoC has developed a bus monitor that will terminate transactions if it detects behavior that breaks rules set by a system designer.
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February 18, 2019

UltraSoC scales up debug architecture

UltraSoC has increased the capacity of its embedded analytics architecture to encompass large-scale manycore architectures.
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October 17, 2018

UltraSoC combines tools for cross-SoC debug and analysis

Following deals with Imperas and Percepio, UltraSoC has released an IDE aimed at debug, run control, performance tuning and runtime analytics for SoC development.
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May 1, 2018

Andes teams with Imperas and UltrasoC for RISC-V

Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
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January 28, 2018

UltraSoC delivers trace for RISC-V

UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , ,   |  Organizations:

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