This week’s RISC-V Summit in California has seen an expansion to the open-source portfolio being built around the architecture as well as increased support from software vendors such as Wind River.
UltraSoC has said it will offer an open-source implementation of its RISC-V trace encoder though the OpenHW Group, arguing the availability of a production-grade, standards-compliant processor trace solution will be a key enabler for developers. The OpenHW Group’s overall aim is to build an open, commercial grade ecosystem for development based on open-source processors.
Rupert Baines, CEO of UltraSoC, said: “We fully believe in industry standards and the importance of open-source; by donating this encoder we can help industry adoption of RISC-V, strengthen the ecosystem and support compatibility and consistency. Open-source is a familiar model in the software world, but in hardware we’re just beginning to unlock the possibilities of this powerful approach. The RISC-V ISA has provided initial momentum, and industry bodies such as the OpenHW Group are now taking it a step further. At the same time, the legal framework has developed to allow hardware IP companies to confidently license their technologies.”
The open-source RISC-V trace is designed to be fully compatible with the processor trace standard currently being developed within the RISC-V Foundation’s Processor Trace Working Group. UltraSoC developed the original RISC-V trace encoding algorithm in 2016, donating the specification as open-source shortly afterwards; pre-standard implementations of the specification are already shipping. The open-source implementation will be made available at the end of Q1 2020 and includes the core functionality expected to be included in the standard. UltraSoC will provide a full commercial offering providing access to additional features such as multiple retirement, out-of-order trace, cycle-accurate tracing, and the filters and counters required for more complex performance analysis.
The OpenHW Group itself has said it has started work on multicore SoC design based around NXP Semiconductor’s iMX platform that will be used to evaluate RISC-V processors in the context of a heterogeneous compute architecture. The Core-V Chassis will combine 64bit and 32bit RISC-V cores with 3D and 2D GPUs, MIPI DSI and CSI, PCIe and gigabit ethernet ports, hardware security blocks, and support for DDR4 memory. The main 64bit core will be based on the PULP design developed at ETH Zurich.
OpenHW Group President and CEO Rick O’Connor said: “The CORE-V Chassis project will help validate that serious silicon development is possible utilizing the ethos of open-source hardware, IP and tools. With the tape out of a functional evaluation SoC during the second half of 2020, we will demonstrate that the open hardware mindset is as capable and dependable as any of today’s closed-source alternatives.”
Custom-processor specialist Codasip said it has become Western Digital’s preferred provider of hardware implementation packages and expert technical support for the open-source SweRV Core EH1. The SweRV Support Package (SSP) provides a set of components to support the design, implementation, test, and software creation for a SweRV Core-based SoC.
Imperas has released its latest update to the RISC-V compliance test suite for the RV32I base RISC-V configuration. Developed in conjunction with the RISC-V Foundation's Technical Committee task group for compliance, the company said it has now achieved an almost 100 per cent functional coverage of the instructions in the RISC-V ISA base specification.
RTOS provider Wind River has launched a support package for RISC-V and joined the RISC-V Foundation. Adding RISC-V support for VxWorks comes on the heels of a number of recent changes to the RTOS, including adoption of the LLVM toolchain, which enables ready support for languages such as C++17, Boost, Python, and the Rust collection of technologies.