DVCon US 2020 preview: SmartDV

By TDF Editor |  No Comments  |  Posted: February 24, 2020
Topics/Categories: Blog - IP, - Verification  |  Tags: , , , , , , ,  | Organizations: ,

STOP PRESS: Please note that DVCon US has been shorted by a day because of the COVID-19 outbreak and will now end on Wednesday, March 4. An updated conference program is available here. Please use it to confirm whether events you plan to join have been moved or cancelled. Delelgates should also visit the DVCon US for details on healthcare protocols they are asked to follow.

Verification and design IP specialist SmartDV will exhibit during DVCon US (DoubleTree Hotel, San Jose, March 2-4) at Booth #304, discussing its portfolio’s support for simulation, emulation, FPGA prototyping, post-silicon validation, formal verification and RISC-V.

Two product highlights will be the company’s new verification and design IP for the MIPI I3C v1.1 utility and control bus specification, and its design IP for DDR5 and LPDDR5 SDRAM controllers

The MIPI I3C 1.1 IP portfolio is configurable, interoperable and reusable for standard interfaces based on hardware verification languages, including SystemVerilog and SystemC. Each component is designed for simplicity of use and comes with advanced commands, configurations and a status reporting interface. The IP can be customized to meet specific needs.

Extending to the latest DDR5 and LPDDR5 specifications, SmartDV’s design IP targets low power and latency as well as reduced gate counts for increased memory interface bandwidth. The IP can be applied to a range of applications. These include high-performance computing, networking, wearables, the Internet of Things and mobile. It can be  customized to meet specific user needs.

Regular demonstrations will also be offered of SmartDV’s Smart ViPDebug protocol debugger. These will aim to showcase how it reduces debug time by identifying violations, and reduces the time needed to find the cause of violations through a linked waveform and transaction database.

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