Tech Design Forum
Briefing
congestion
congestion
July 14, 2023
Cadence mixes know-how and AI to bridge RTL gap
The Joules RTL Design Studio aims to make coding more aware of aware of physical issues before and after hand-off for implementation.
Article | Topics:
Blog Topics
,
Physical design
,
RTL
,
Verification
| Tags:
AI
,
congestion
,
debug
,
generative AI
,
PPA
,
what if
| Organizations:
Alibaba
,
Arm
,
Cadence Design Systems
,
MediaTek
January 5, 2015
Cadence high-level synthesis changes deal with congestion
SystemC coding style can lead to excessive congestion in the logic generated by high-level synthesis. Cadence described how it is attacking the issue at its recent Front-End Design Summit.
Article | Topics:
Blog - EDA
| Tags:
14nm/16nm
,
cell pin access
,
congestion
,
high level synthesis (HLS)
,
physical synthesis
,
routing
| Organizations:
Cadence Design Systems
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