Breker CEO Adnan Hamid will lead a tutorial on the Portable Stimulus Standard as part of the verification specialist's activities in Shanghai.
Tech Design Forum talked to the general and program chairs of DVCon Europe about the conference and how it seeks to show the expansion of IC verification methodologies to the system level.
Verification of SoCs can't be done by adapting IP-level strategies - it'll take a much greater interaction with software, and the use of a shared language
Cadence has released a tool intended to ease the creation of scenario-driven tests to better exercise complex IP and SoC designs.
Carbon Design Systems has introduced a web portal to streamline the process of finding the most appropriate executable models for a system-level virtual prototype.
Can applications provide useful input for verification? They can but not when run straight out of the box, panelists at DAC 2014 said.
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