January 28, 2018
UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.
January 23, 2018
Struggling with how to make your debug triage process more efficient? A new checklist could help focus your efforts.
October 17, 2017
Mentor will present seven papers during the ARMTech Con and a dedicated session, and exhibit at Booth #606.
June 19, 2017
UltraSoc has donated to the RISC-V Foundation a specification for processor trace to try to provide the ecosystem with a common way of exporting runtime data to software tools.
April 28, 2017
ARM is using technologies such as Hadoop and Spark to provide insight into how well its verification processes are working.
December 7, 2016
HiSilicon has licensed UltraSoC’s semiconductor IP to build into SoCs for system monitoring, analysis, and optimization.
November 24, 2016
Codasip, a provider of processor cores based on the open-source RISC-V processor IP, has teamed up with UltraSoC to incorporate hardware debug and security features.
September 20, 2016
UltraSoC plans to support the RISC-V open-source instruction architecture with its debug infrastructure and tools.
February 25, 2016
Mentor Graphics is looking to get yet more efficiency from its market-leading Veloce emulator family through an OS upgrade and new task-specific Apps.
December 1, 2015
Ultrasoc is adding security monitoring to its toolkit, providing SoC designers with a mechanism for their chips to warn of attempts by hackers to break into secure areas.