February 18, 2019
UltraSoC has increased the capacity of its embedded analytics architecture to encompass large-scale manycore architectures.
February 11, 2019
DVCon USA is coming soon. Mentor's 2019 involvement includes a keynote from parent Siemens and a tutorial on managing your formal verification processes.
October 29, 2018
As ITC 2018 begins, Mentor addresses stringent ISO 26262 requirements and looks to bridge the gap in how IJTAG-based debug is structured.
October 17, 2018
Following deals with Imperas and Percepio, UltraSoC has released an IDE aimed at debug, run control, performance tuning and runtime analytics for SoC development.
June 21, 2018
Real Intent's move into post-synthesis CDC debug leads its DAC 2018 activities, with technical papers on its new Verix PhyCDC tool also now online for those who cannot make it.
May 22, 2018
Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.
May 1, 2018
Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
February 20, 2018
The formal verification specialist will leverage its recent, successful certification by TÜV SÜD for functional safety solutions.
January 28, 2018
UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.
January 23, 2018
Struggling with how to make your debug triage process more efficient? A new checklist could help focus your efforts.