Following the acquisition of Jasper Design Automation last year, Cadence Design Systems is widening the target base of applications for formal verification, covering tasks from bug hunting through accelerated simulation to 'superlinting'.
Technology from Duolog acquisition used to ease the configuration of interconnect, debug and trace - and the integration of third-party IP
Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.
Cadence Design Systems has launched a debug tool designed to improve the speed of bug hunting in SystemVerilog but which the company expects to grow into analog and post-silicon work.
UltraSoC has added the ability to employ a USB 2.0 port instead of JTAG as the main debug access point on SoCs that use the company’s UltraDebug technology.
New portfolio integrates and extends existing industrial embedded tools to meet the demands of Industry 4.0
A multiprocessor test chip has led ARM to improve the energy-control strategy for its Big.Little architecture and to simplify the debug architecture for the company's multicore processor IP.
Major overhaul of clock domain crossing suite adds configurable debugger, boosts performance by 30% and cuts memory 40% for 'giga-scale' designs.
Synopsys is integrating its verification tools to make it easier to move between verification approaches for software centric SoCs
Can applications provide useful input for verification? They can but not when run straight out of the box, panelists at DAC 2014 said.
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