Achronix is introducing an FPGA architecture that pulls a full network-on-chip into the programmable-logic fabric combined with hardened matrix-math processors for AI.
Cadence Design Systems has released a set of ten verification IP packages intended to support a new crop of standard protocols.
High powered alliance develops TLM standards to address growing automotive and IoT concerns.
Vendor adds verification support for 25G, 50G and 100G Ethernet through emulator-based virtualization.
Xmos has launched a series of microcontrollers based on its timesliced multicore architecture that adds Gigabit Ethernet interfaces.
Test and Verification Solutions has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.
Synopsys has rolled out its SystemVerilog-based verification IP portfolio for a bunch of interconnect standards – and built in support for all the three major verification methodologies.
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