Tech Design Forum
Briefing
protocol debug
protocol debug
February 24, 2020
DVCon US 2020 preview: SmartDV
The latest in MIPI and DDR design and verification IP as well as protocol debug are highlights in SmartDV's DVCon program.
Article | Topics:
Blog - IP
,
- Verification
| Tags:
DDR5
,
debug
,
LPDDR5
,
MIPI
,
protocol debug
,
RISC-V
,
verification IP
,
VIP
| Organizations:
DVCon US
,
SmartDV
Briefing Topics
EDA
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Electrical Design
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IP
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