Verification platform offers unified compile, debug environments
Synopsys is integrating its verification tools to make it easier to move between verification approaches for software centric SoCs
debug
Applications won’t find all the bugs, but they have their uses
Can applications provide useful input for verification? They can but not when run straight out of the box, panelists at DAC 2014 said.
Synopsys speeds HAPS prototyping with ProtoCompiler
HAPS-specific enhancements to Synplify and Certify join next gen partitioning and planning in suite that claims 3X boost in time-to-prototype
Real Intent’s Ascent XV at the ‘fuzzy’ boundary between design and verificiation
Upgrade to Ascent XV X-propagation and reset optimization tool claims 10X runtime gain, deeper reporting, further integration with Verdi and more.
Synopsys targets 5X performance gain with integrated verification suite
New tool technologies, Verdi integration and greater flow concurrency also contribute to a claimed 3X increase in productivity for Verification Compiler.
Real Intent state machine debug focuses on core errors
Real Intent' Ascent IIV tool adds analysis functions to pinpoint fundamental errors in finite state machines and support for SystemVerilog 2009.
Altera and ARM unite FPGA and processor debug
Altera has cut a deal with ARM to bring unified debug support to the FPGA fabric and Cortex-A9 processors inside the Cyclone SoC products, using a specialized version of ARM’s DS5 tool.
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