debug

December 1, 2015

Ultrasoc tweaks debug technology to act as SoC burglar alarm

Ultrasoc is adding security monitoring to its toolkit, providing SoC designers with a mechanism for their chips to warn of attempts by hackers to break into secure areas.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , ,   |  Organizations:
November 11, 2015

UltraSoC adds CoreSight and Ceva debug support

UltraSoC is extending its debug support for a variety of processor cores through compatibility with ARM’s CoreSight debug system as well as support for Ceva’s DSP cores.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , , ,   |  Organizations: , ,
September 16, 2015

Synopsys extends FPGA-based prototyping to 1.6bn ASIC gates

Synopsys updates its FPGA-based prototyping system to offer more capacity, higher speed, faster bring-up, better ROI
Article  |  Topics: Blog - IP, - Verification  |  Tags: , , , ,   |  Organizations:
September 10, 2015

Debug monitors look for deadlock

UltraSoC has added deadlock detection capabilities to its multicore onchip debug framework.
Article  |  Topics: Blog - Embedded  |  Tags: , ,   |  Organizations:
June 9, 2015

Debug life cycle expands with on-chip infrastructure

By widening the range of resources that can be tracked within an SoC, Ultrasoc says it has uncovered ways to make debug a long-term tool for complex multicore designs.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , , , ,   |  Organizations:
June 8, 2015

Formal integration enhances bug-hunting for Cadence

Following the acquisition of Jasper Design Automation last year, Cadence Design Systems is widening the target base of applications for formal verification, covering tasks from bug hunting through accelerated simulation to 'superlinting'.
June 3, 2015

ARM eases interconnect, debug, third-party IP integration for SoCs

Technology from Duolog acquisition used to ease the configuration of interconnect, debug and trace - and the integration of third-party IP
Article  |  Topics: Blog Topics  |  Tags: , , ,   |  Organizations: ,
May 21, 2015

Real Intent tackles CDC at the physical level

Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.
April 28, 2015

Cadence upgrades debug for system-level era

Cadence Design Systems has launched a debug tool designed to improve the speed of bug hunting in SystemVerilog but which the company expects to grow into analog and post-silicon work.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations:
April 22, 2015

UltraSoC pushes debug over USB

UltraSoC has added the ability to employ a USB 2.0 port instead of JTAG as the main debug access point on SoCs that use the company’s UltraDebug technology.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , ,   |  Organizations:

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