Ultrasoc is adding security monitoring to its toolkit, providing SoC designers with a mechanism for their chips to warn of attempts by hackers to break into secure areas.
UltraSoC is extending its debug support for a variety of processor cores through compatibility with ARM’s CoreSight debug system as well as support for Ceva’s DSP cores.
Synopsys updates its FPGA-based prototyping system to offer more capacity, higher speed, faster bring-up, better ROI
UltraSoC has added deadlock detection capabilities to its multicore onchip debug framework.
By widening the range of resources that can be tracked within an SoC, Ultrasoc says it has uncovered ways to make debug a long-term tool for complex multicore designs.
Following the acquisition of Jasper Design Automation last year, Cadence Design Systems is widening the target base of applications for formal verification, covering tasks from bug hunting through accelerated simulation to 'superlinting'.
Technology from Duolog acquisition used to ease the configuration of interconnect, debug and trace - and the integration of third-party IP
Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.
Cadence Design Systems has launched a debug tool designed to improve the speed of bug hunting in SystemVerilog but which the company expects to grow into analog and post-silicon work.
UltraSoC has added the ability to employ a USB 2.0 port instead of JTAG as the main debug access point on SoCs that use the company’s UltraDebug technology.
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