July 30, 2020
Arm works with EDA to find new efficiencies based on extra CTL-based check in Questa runs.
January 29, 2020
Deadlock is hard to detect even though there are formal strategies for doing so. But wouldn't it be better if you could automate that work? Now you can.
May 2, 2017
DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.
September 10, 2015
UltraSoC has added deadlock detection capabilities to its multicore onchip debug framework.
June 9, 2014
Can applications provide useful input for verification? They can but not when run straight out of the box, panelists at DAC 2014 said.
May 28, 2014
NetSpeed Systems aims to cut SoC integration time using theories developed for much larger computer networks.
February 26, 2014
Real Intent' Ascent IIV tool adds analysis functions to pinpoint fundamental errors in finite state machines and support for SystemVerilog 2009.
October 17, 2012
New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.