Arm works with EDA to find new efficiencies based on extra CTL-based check in Questa runs.
Deadlock is hard to detect even though there are formal strategies for doing so. But wouldn't it be better if you could automate that work? Now you can.
DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.
UltraSoC has added deadlock detection capabilities to its multicore onchip debug framework.
Can applications provide useful input for verification? They can but not when run straight out of the box, panelists at DAC 2014 said.
NetSpeed Systems aims to cut SoC integration time using theories developed for much larger computer networks.
Real Intent' Ascent IIV tool adds analysis functions to pinpoint fundamental errors in finite state machines and support for SystemVerilog 2009.
New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.
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