The latest in MIPI and DDR design and verification IP as well as protocol debug are highlights in SmartDV's DVCon program.
Faster, lower power flash interface IP with built-in encryption/decryption speeds access to embedded and removable storage.
Synopsys' line-up at next week's ARM TechCon includes joint presentations with Huawei and Nvidia.
Cadence Design Systems has released a set of ten verification IP packages intended to support a new crop of standard protocols.
Test and Verification Solutions has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.
Cadence Design Systems has decided to buy Poland-based IP developer Evatronix as part of a plan to round out its portfolio of interfaces for SoC designs.
Cadence Design Systems is to buy Cosmic Circuits Private Limited, a developer of analog and mixed signal intellectual property (IP) cores.
Synopsys has rolled out its SystemVerilog-based verification IP portfolio for a bunch of interconnect standards – and built in support for all the three major verification methodologies.
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