post-silicon debug


October 8, 2019

UltraSoC adds security checks to bus monitoring IP

UltraSoC has developed a bus monitor that will terminate transactions if it detects behavior that breaks rules set by a system designer.
Article  |  Topics: Blog - IP  |  Tags: , ,   |  Organizations:
January 28, 2018

UltraSoC delivers trace for RISC-V

UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , ,   |  Organizations:
December 1, 2015

Ultrasoc tweaks debug technology to act as SoC burglar alarm

Ultrasoc is adding security monitoring to its toolkit, providing SoC designers with a mechanism for their chips to warn of attempts by hackers to break into secure areas.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , ,   |  Organizations:
June 9, 2015

Debug life cycle expands with on-chip infrastructure

By widening the range of resources that can be tracked within an SoC, Ultrasoc says it has uncovered ways to make debug a long-term tool for complex multicore designs.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , , , ,   |  Organizations:
June 9, 2014

Applications won’t find all the bugs, but they have their uses

Can applications provide useful input for verification? They can but not when run straight out of the box, panelists at DAC 2014 said.
October 9, 2013

Jasper preps User Group and Architectural events

The EDA vendor has set a broad agenda across two Silicon Valley events taking place in late October, with registration now open for both.
Article  |  Topics: Blog Topics, Conferences  |  Tags: , , , ,   |  Organizations:

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