The best paper awards at this month's DVCon highlighted techniques to streamline verification. The European version in the meantime is looking for paper submissions.
Recent developments have made Open-RAN look more attractive as a way of implementing 5G systems. This is helping to drive a shift-left in verification and test.
Siemens has agreed to acquire UK-based debug and on-chip instrumentation startup UltraSoC and will fold the operation into Mentor’s Tessent test-software product line.
Papers presented at the recent IRPS conference showed the growing importance of lifetime monitoring to the problem of handling components as they age.
UltraSoC and Agile Analog have teamed up to build an infrastructure that can help guard against physical attacks on SoCs.
UltraSoC has kicked off a collaboration with PDF Solutions to build a system better able to use runtime information to identify devices that are likely to fail in the field and so reduce the impact of product recalls.
UltraSoC has developed a bus monitor that will terminate transactions if it detects behavior that breaks rules set by a system designer.
UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.
Ultrasoc is adding security monitoring to its toolkit, providing SoC designers with a mechanism for their chips to warn of attempts by hackers to break into secure areas.
By widening the range of resources that can be tracked within an SoC, Ultrasoc says it has uncovered ways to make debug a long-term tool for complex multicore designs.
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