UltraSoC has developed a bus monitor that will terminate transactions if it detects behavior that breaks rules set by a system designer.
UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.
Ultrasoc is adding security monitoring to its toolkit, providing SoC designers with a mechanism for their chips to warn of attempts by hackers to break into secure areas.
By widening the range of resources that can be tracked within an SoC, Ultrasoc says it has uncovered ways to make debug a long-term tool for complex multicore designs.
Can applications provide useful input for verification? They can but not when run straight out of the box, panelists at DAC 2014 said.
The EDA vendor has set a broad agenda across two Silicon Valley events taking place in late October, with registration now open for both.
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