PCIe


May 28, 2021

PCIe 6.0 gets verification IP as formal arrival approaches

Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
Article  |  Topics: Blog - EDA, IP, - Verification  |  Tags: , , , , , , ,   |  Organizations: ,
January 22, 2021

How to use virtual mode in emulation

Virtual strategies make for greater productivity and widen the number of emulation use cases. A new paper considers some of the most popular examples.
February 13, 2018

HyperLynx update automates SerDes validation

Simulation suite automates the largely manual process of validating more than 25 SerDes protocols.
Article  |  Topics: Blog Topics, Blog - PCB, - Product  |  Tags: , , , , , ,   |  Organizations:
May 3, 2017

Master the verification challenge of PCIe-based NVMe storage

NVMe is driving the SSD market thanks to its many useful features, but at least five major challenges must inform your verification plan.
Article  |  Topics: Blog - EDA, - Standards, Verification  |  Tags: , , , ,   |  Organizations: ,
February 8, 2013

Cadence buys IP provider Cosmic

Cadence Design Systems is to buy Cosmic Circuits Private Limited, a developer of analog and mixed signal intellectual property (IP) cores.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
February 27, 2012

Synopsys verification IP launch has bite

Synopsys has rolled out its SystemVerilog-based verification IP portfolio for a bunch of interconnect standards – and built in support for all the three major verification methodologies.

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