January 29, 2020
Deadlock is hard to detect even though there are formal strategies for doing so. But wouldn't it be better if you could automate that work? Now you can.
May 8, 2019
Cadence and OneSpin are applying various forms of machine learning to their tools to automate formal verification.
October 17, 2018
The latest Mentor-commissioned Wilson Research Group study on ASIC and FPGA verification highlights technique adoption and maturity.
May 31, 2015
Senior verification expert at Imagination Technologies debunks ten myths surrounding the use of formal techniques in SoC design and verification
May 11, 2015
Conference addresses formal verification techniques at levels to suit beginners through to experts
October 17, 2012
New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.