UC Berkeley


June 27, 2018

Remember the design gap? It’s back

Fifteen years on from the design gap that triggered the IP revolution, implementation costs have created a new one.
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June 20, 2018

SAR-VCO combo tunes RF receiver power on 16nm

Researchers from the UC Berkeley and Intel teamed up to develop an energy-tuneable RF front-end on a digital finFET process with no need for analog process options.
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April 9, 2018

DAC keynotes and sessions aim for AI

DAC in June will feature a series of keynotes and technical sessions on machine learning and AI for both target applications and in the design process itself.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations: , , ,
April 7, 2016

SNUG 2016: Intel, TSMC, GloFo back post-finFET research at UC Berkeley

But project lead Chenming Hu, 'finFET's father', has also highlighted important changes in the funding landscape for university research.
March 11, 2016

GSA on how to reinvigorate silicon business models

Open-source hardware, in-field configurability, and a hardware-plus-services approach could protect margins as the IoT hammers down costs, says GSA report.
August 9, 2014

Particle-collider technology to help NI build time-aware systems

Technology from advanced-physics research institute CERN will form part of National Instruments' long-term strategy to improve the ability of distributed systems to support real-time control.
June 3, 2013

CMOS “good for another century,” says father of finFET

CMOS approaches are likely to underpin electronics for the next century, according to Chenming Hu, father of the finFET
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March 12, 2013

EDA sets sail in a ‘sea of processors’

The purchase of Tensilica by Cadence Design Systems could prove the way that EDA and multicore-based system design come together.
December 10, 2012

Oxygen injection for go-faster 14nm transistors

Mears Technologies and UC Berkeley describe at IEDM 2012 how oxygen in a silicon superlattice could boost performance beyond strained silicon at 14nm.
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