1D routing


June 22, 2018

Imec stacks transistors for denser 3nm option

Imec proposes using stacked CMOS transistors and buried power rails to improve density for the 3nm process node.
Article  |  Topics: Blog Topics  |  Tags: , , , , ,   |  Organizations:
March 26, 2014

Even EUV faces a 1D future, says IMEC

IMEC's Rudy Lauwereins explained at DATE 2014 how 1D routing for self-aligned multiple patterning is likely to be inevitable even if EUV makes it into production fabs.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:

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