research


February 25, 2019

China Focus 2: The Design Dilemma

Do China's ambitions as a world-class innovator face fundamental challenges as a result of the sector's existing economic infrastructure?
October 17, 2018

FPGA playing verification catch-up as bugs escape

The latest Mentor-commissioned Wilson Research Group study on ASIC and FPGA verification highlights technique adoption and maturity.
Article  |  Topics: Verification  |  Tags: , , , , , ,   |  Organizations: ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors