DFM

July 29, 2020

Litho hotspot analysis gets machine-learning turbocharge

A Mentor-Samsung collaboration cuts the need for model-based analysis and speeds analysis runtime by as much as 20X.
Article  |  Topics: Case Study, Conferences, Design to Silicon  |  Tags: , , , ,   |  Organizations: , ,
December 18, 2019

On-demand DRC within P&R cuts closure time in half for MaxLinear

Case study describes how RF/AMS specialist used Calibre RealTime Digital within its flow for a high-end DSP SoC.
November 15, 2018

Xpedition updated for schematic verification and DFT

Mentor's flagship PCB suite is aiming to offer another 'shift left' in verification as respins rise.
Article  |  Topics: Blog - PCB  |  Tags: , , , , ,   |  Organizations:
September 12, 2018

Mentor automates silicon photonics layout

The LightSuite Compiler produces designs based on Python descriptions and certifies them DRC-clean through hooks into the market-leading Calibre DFM suite.
March 23, 2018

Layout schema generation speeds early-stage yield learning

LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.
March 9, 2018

DATE 2018 preview: Mentor

DATE highlights for Mentor include a 90-minute workshop on achieving functional safety for autonomous driving.
June 20, 2017

Siemens sees Mentor helping to build fast digital twins

An emulator that extends the reach of hardware acceleration into the world of multiphysics analysis could result from the merger of Siemens PLM Software with Mentor.
Article  |  Topics: Blog - EDA, Electrical Design, Embedded, PCB  |  Tags: , , , , , , , ,   |  Organizations: ,
June 1, 2016

Samsung taps Mentor for Closed-Loop DFM

Samsung Foundry has adapted Mentor's DFM and test tools in a system that can produce a 10% increase in yield across all nodes.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: ,
April 5, 2016

Cadence moves into safer design with Virtuoso changes

Cadence Design Systems has made additions to its Virtuoso mixed-signal design environment intended to improve design for manufacture and the ability of teams to create and test safety-critical systems.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
October 6, 2015

Samsung taps Mentor tools for higher yielding close-loop DFM

Samsung bases PRISM and FLARE defect analysis and optimization on Mentor Graphics' Calibre and Tessent. Yields rise. Ramps shorten.

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