On-demand DRC within P&R cuts closure time in half for MaxLinear
Case study describes how RF/AMS specialist used Calibre RealTime Digital within its flow for a high-end DSP SoC.
DFM
Xpedition updated for schematic verification and DFT
Mentor's flagship PCB suite is aiming to offer another 'shift left' in verification as respins rise.
Mentor automates silicon photonics layout
The LightSuite Compiler produces designs based on Python descriptions and certifies them DRC-clean through hooks into the market-leading Calibre DFM suite.
Layout schema generation speeds early-stage yield learning
LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.
DATE 2018 preview: Mentor
DATE highlights for Mentor include a 90-minute workshop on achieving functional safety for autonomous driving.
Siemens sees Mentor helping to build fast digital twins
An emulator that extends the reach of hardware acceleration into the world of multiphysics analysis could result from the merger of Siemens PLM Software with Mentor.
Samsung taps Mentor for Closed-Loop DFM
Samsung Foundry has adapted Mentor's DFM and test tools in a system that can produce a 10% increase in yield across all nodes.
Cadence moves into safer design with Virtuoso changes
Cadence Design Systems has made additions to its Virtuoso mixed-signal design environment intended to improve design for manufacture and the ability of teams to create and test safety-critical systems.
Samsung taps Mentor tools for higher yielding close-loop DFM
Samsung bases PRISM and FLARE defect analysis and optimization on Mentor Graphics' Calibre and Tessent. Yields rise. Ramps shorten.
Cadence updates Allegro with PCB production and routing tools
Cadence has launched the 16.6 release of its Allegro PCB-design portfolio, adding modules for manufacturing documentation and design-rule preparation aids.
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