Adding an MOL layer that takes advantage of a self-aligned pitch-splitting technique and a rotated layout could cut standard-cell height to 4T.
Mentor, a Siemens business, plans to expand the team working on the Aprisa place-and-route tool following the purchase of Avatar Integrated Systems, announced in July.
Imec proposes using stacked CMOS transistors and buried power rails to improve density for the 3nm process node.
At VLSI Symposia 2018, GlobalFoundries researchers proposed looking at the metal-gate ‘gear’ ratio as a way of improving the routability of standard cells.
Collaboration between ARM, TSMC and Synopsys reveals challenges of 10nm finFET design flows.
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