IEDM to examine scaling from multiple directions

Two late-news papers to be presented at the upcoming International Electron Device Meeting (IEDM) will describe two directions in nanometer scaling, with one tackling the steps towards developing 3nm CMOS and another dealing with DRAM scaling to 16nm and beyond.

At the December conference in San Francisco, Samsung researchers will describe their 3nm CMOS technology based on gate-all-around (GAA) transistors, constructed using horizontal nanosheets. Samsung claims its “multi-bridge-channel” architecture is highly manufacturable as it can be implemented using the company’s existing finFET fabrication technology with a few revised photomasks. Direct patterning supports different nanosheet channel widths for design flexibility, according to Samsung.

For the conference paper, the team built a fully functioning high-density SRAM macro and claim the process demonstrates high gate controllability, with 65 mV/dec subthreshold swing and 31 per cent higher on-current than the company’s finFET technology.

Scaling of DRAM below 20nm presents other issues, but Imec researchers will claim at IEDM that there are ways to manage it. They used atomic layer deposition (ALD) to pattern and build a novel 11nm pillar-shaped capacitor using novel dielectric materials based on an oxide of strontium and titanium to achieve a high dielectric constant. This should make it possible to store a usable charge in such a small structure.

An alternative to DRAM for SoCs is magnetic RAM, which has the additional advantage of non-volatility. Intel will describe how it is adding e-MRAM to a 22nm finFET process. For the work The magnetic tunnel junction-based memory cells are built from dual MgO magnetic tunnel junctions (MTJs) separated by a CoFeB-based layer in a one-transistor/one-resistor (1T-1R) configuration in the interconnect stack. To demonstrate their performance, Intel built 7.2 Mb MRAM arrays which achieved data retention of ten years with a less than one in a million error rate at 200ºC and a write endurance of more than a million cycles.

Although circuits can still scale down, energy consumption remains a major obstacle. The exploitation of negative capacitance in ferroelectric stacks may make it possible to improve the subthreshold swing of CMOS transistors and with that reduce power drawn during switching.

A team led by Taiwan’s National Nano Device Laboratories will discuss how they used a thermal-ALD process to build an HZO ferroelectric gate insulator in 60nm-gate length finFETs that appear able to take advantage of this phenomenon. The researchers claim the insertion of a ferroelectric into the gate stack does not negatively impact switching speed: with cutoff frequencies exceeding 23GHz and a gate delays of 143ps. To evaluate performance, the researchers used them to build circuit building blocks: integrated inverters, ring oscillators, and SRAM test cells.