EDA

December 6, 2021

DAC 2021 preview: Breker Verification Systems

Breker will highlight its latest work on stress-testing processor, storage and I/O architectures during DAC 2021 this week.
December 3, 2021

DAC 2021 preview: Verific

Tool development enabler Verific will demonstrate its parsers, including a combination with the INVIO API platform at DAC 2021 in San Francisco next week.
Article  |  Topics: Conferences, Tool development, Verification  |  Tags: , , , , , , ,   |  Organizations: ,
December 3, 2021

DAC 2021 preview: SmartDV

The design and verification IP specialist will present its full range, including the Smart Compiler, at next week's Design Automation Conference.
Article  |  Topics: Conferences, Digital/analog implementation, Blog - EDA, - RTL, Verification  |  Tags:   |  Organizations: ,
November 23, 2021

DAC 2021 Preview: Siemens EDA

DAC 2021 is looming and here is our first round up of a major EDA player's plans for the physical event in San Francisco.
November 17, 2021

Balancing the requirements of E/E architectures for automotive design

A new white paper examines how to develop architectures around the main E/E elements placing growing demands on automotive engineering teams.
November 5, 2021

UK consortium starts work on cryogenic CMOS

A £6.5m grant will fund the development of memories and other IP to improve the control of qubits in quantum computers.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: , ,
November 4, 2021

Design management survey points to more tactical cloud EDA

Cloud computing is gaining ground in EDA but close to a third of organizations are planning to stay with on-premises computing for the foreseeable future, according to a survey commissioned by IC Manage.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:
November 3, 2021

Python provides the link for speed checks at Sondrel

Sondrel has combined EDA tools with custom SystemC and Python code to develop a system that can help automate the detailed performance analysis of high-level architectures before RTL is generated.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations: ,
November 2, 2021

Glitch detection cores add to Agile portfolio

Agile Analog has moved into the supply of cores for detecting hardware-hacking attempts as well as more conventional data-conversion modules.
Article  |  Topics: Blog - IP  |  Tags: , ,   |  Organizations:
October 27, 2021

DVCon Europe explores pitfalls and possibilities of AI for verification

In a panel at this week’s DVCon Europe, experts described a number of issues facing teams looking to incorporate machine learning in logic verification flows and why some of those efforts will not pay off while others succeed.

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