sequential equivalence checking


February 28, 2020

Learn how Renesas uses SLEC to enhance its verification flows

A new technical article discusses Renesas' addition of SLEC to its SystemC and RTL flows and the improvements it achieved in time and coverage..
Article  |  Topics: Blog - EDA, - HLS  |  Tags: , , ,   |  Organizations: ,
May 24, 2019

OneSpin extends line-up for AI FPGA and RISC-V verification

The formal specialist is extending its line for Intel FPGAs that target areas such as AI/ML and HPC, and building out a RISC-V suite focused on ISA compliance.

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