EDA

July 7, 2022

DAC 2022 preview: Breker Verification Systems

Breker's presence at next week's Design Automation Conference (DAC) will emphasize a new collaboration around the RISC-V platform.
Article  |  Topics: Blog Topics  |  Tags: , , , , ,   |  Organizations: ,
July 7, 2022

DAC 2022 preview: Verific Design Automation

The tool development specialist will demonstrate its broad portfolio at next week's Design Automation Conference in San Francisco.
Article  |  Topics: Blog - EDA, - Tool development  |  Tags: , , , ,   |  Organizations: ,
June 28, 2022

Coherency verification for CXL

CXL is a strongly-backed technology aimed at improving connectivity across datacenters handling high demand HPC and AI applications.
June 16, 2022

TSMC certifies Aprisa for N5 and N4

TSMC has certified the Aprisa place-and-route software from Siemens Digital Industries Software for the N5 and N4 process technologies.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
June 13, 2022

Real Intent updates reset and clock-domain crossing tools

Real Intent has upgraded its Meridian CDC clock-domain crossing sign-off tool, with support for multimode-aware dynamic models.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
June 10, 2022

Cadence adds machine learning to electrical simulation

Cadence has used machine-learning techniques originally developed for its Cerebrus tool to build software that can speed up multiphysics analysis.
Article  |  Topics: Blog - EDA, Electrical Design  |  Tags: , , ,   |  Organizations:
May 25, 2022

Siemens brings ReadyStart RTOS to RISC-V

Siemens has expanded its Nucleus ReadyStart program to the RISC-V architecture.
Article  |  Topics: Blog - Embedded  |  Tags: , , , ,   |  Organizations:
May 24, 2022

Saber models aim for ADI power chips

Synopsys and Analog Devices have agreed to provide model libraries for the chipmaker's DC/DC ICs and power regulators that work with the Saber simulation tool.
Article  |  Topics: Blog - IP  |  Tags: , ,   |  Organizations: ,
May 12, 2022

Extended coverage for sign-off analysis

Real Intent has extended the fault coverage of its Meridian DFT static sign-off tool with improvements to the reporting of issues and the ability to track down root causes.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
April 29, 2022

Navigate variables and lifetimes in SystemVerilog

Variable lifetimes are an apparently basic but also tricky feature within the verification language.
Article  |  Topics: Verification  |  Tags: , , , , ,   |  Organizations: ,

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