Imperas and Synopsys team on RISC-V debug
Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
EDA
Siemens harnesses machine learning for more comprehensive verification
As first silicon success declines, new software aims to provide a more holistic view of coverage data from multiple sources.
RISC-V gets verification and security IP additions
Ahead of the RISC-V Summit in San Jose, Imperas Software has issued updates to its ImperasDV verification IP for RISC-V verification and Codasip has launched a secure-processor initiative.
Identifying AI opportunities in PCB design
The key to exploiting AI is being clear about where its family of technologies can help to improve and democratize design.
Siemens aims to simplify compliance for Linux medical devices
New Quality Package focuses on safety and cybersecurity compliance with EU and US medical device standards.
Chipletz pushes packaging design for AI, HPC and immersive use-cases
The Austin-based start-up used Siemens EDA software to deploy a cutting-edge Smart Substrate based on advanced packaging technology.
Real Intent tool looks for glitches
Real Intent has developed a tool to check design and the potential for circuits to glitch.
Semiwise brings cryogenic models to SOI
Semiwise has developed transistor models for the GlobalFoundries 22FDX that cover operation at cryogenic temperatures.
Siemens automates test to handle multi-die 2.5D, 3D and 5.5D architectures
Tessent Multi-die extends the capabilities of the DFT suite in line with new standards intended to enable widespread adoption of interposer and stacked die strategies.
Agile Analog adds digital library for easier porting
Agile Analog has launched its own digital standard cell library, designed to be used in the control circuits for analog blocks that form the IP company’s main offering.
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