Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
As first silicon success declines, new software aims to provide a more holistic view of coverage data from multiple sources.
Ahead of the RISC-V Summit in San Jose, Imperas Software has issued updates to its ImperasDV verification IP for RISC-V verification and Codasip has launched a secure-processor initiative.
The key to exploiting AI is being clear about where its family of technologies can help to improve and democratize design.
New Quality Package focuses on safety and cybersecurity compliance with EU and US medical device standards.
The Austin-based start-up used Siemens EDA software to deploy a cutting-edge Smart Substrate based on advanced packaging technology.
Real Intent has developed a tool to check design and the potential for circuits to glitch.
Semiwise has developed transistor models for the GlobalFoundries 22FDX that cover operation at cryogenic temperatures.
Tessent Multi-die extends the capabilities of the DFT suite in line with new standards intended to enable widespread adoption of interposer and stacked die strategies.
Agile Analog has launched its own digital standard cell library, designed to be used in the control circuits for analog blocks that form the IP company’s main offering.
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