EDA

Cadence has given its new release of OrCAD access to the cloud-based AI placer designed for its Allegro PCB-layout software.

Just how much of the flow has already has 'shift left' benefit and what is fueling further progress.

Tessolve is bringing its Verification Futures conference to the US with an event scheduled for mid-September.

The Joules RTL Design Studio aims to make coding more aware of aware of physical issues before and after hand-off for implementation.

The recent Verification Futures Europe conference looked at what AI, from decision trees to foundation models, could do to speed up RTL checks.

Calibre Design Enhancer moves physical verification checks and automated DRC-clean via and cell insertion into P&R

Three fast developing AI techniques underpin the efficiencies in the new Solido custom design and verification platform.

Single-device tracking in the chiplet and multi-chip age needs a boost to deliver accuracy and greater production efficiency.

Siemens is integrating the Supplyframe platform with the Xpedition PCB-design software to give engineers better visibility into component availability.

Siemens has published a white paper that examines whether package designers need to adopt IC tools and design styles in the move from organic packages to 2.5DIC packages.