Module verification demands integrated DRC and LVS
The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.
LVS
Silicon Photonics verification case study from UC-Davis and Texas A&M
Silicon Photonics 3D integration posed LVS challenges in this fast emerging technical space. A case study describes how the two institutions overcame them.
Mentor tunes LVS for early SoC integration
Mentor has released a tool that attempts to deal with the problems encountered in the use of physical circuit verification in the early stages of SoC integration.
EDA in the cloud boosts DRC iterations for AMD
AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.
Video series details the physical verification process
Physical verification challenge of large SoCs on leading-edge processes detailed in video series