Mentor tunes LVS for early SoC integration
Mentor has released a tool that attempts to deal with the problems encountered in the use of physical circuit verification in the early stages of SoC integration.
LVS
EDA in the cloud boosts DRC iterations for AMD
AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.
Video series details the physical verification process
Physical verification challenge of large SoCs on leading-edge processes detailed in video series
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