The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.
Silicon Photonics 3D integration posed LVS challenges in this fast emerging technical space. A case study describes how the two institutions overcame them.
Mentor has released a tool that attempts to deal with the problems encountered in the use of physical circuit verification in the early stages of SoC integration.
AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.
Physical verification challenge of large SoCs on leading-edge processes detailed in video series
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